Infinite


  • Home

  • Categories

  • Archives

  • Tags

  • Sitemap

  • RSS

  • Search

mongoDB 基础

Posted on 2018-01-08 | Post modified 2019-11-16 | In database | Visitors

Basic

  • NoSQL 数据库
  • compass app: 连接 mongodb atlas 的官方 app
  • mongod: mongoDB 的 database application
  • mongo: 提供和 database 进行交互的 shell 接口 application
  • 向 mongodb atlas 上传数据
    1
    mongoimport --type csv --headerline --db mflix --collection movies_initial --host "cluster0-shard-00-00-1cvum.mongodb.net:27017,cluster0-shard-00-01-1cvum.mongodb.net:27017,cluster0-shard-00-02-1cvum.mongodb.net:27017" --authenticationDatabase admin --ssl --username hansonzhao007 --password XXXXXX --file movies_initial.csv
    Read more »

【WEP】CPU Caching

Posted on 2017-10-10 | Post modified 2019-11-16 | In OS | Visitors

hierarchy

Program code and data has temporal and spatial locality. This means that, over short periods of time, there is a good chance that the same code or data gets reused.

For code this means that there are most likely loops in the code so that the same code gets executed over and over again (the perfect case for spatial locality对于刚被访问的数据,其相邻的数据在将来被访问的概率高). Data accesses are also ideally limited to small regions. Even if the memory used over short time periods is not close together there is a high chance that the same data will be reused before long (temporal locality对于刚被访问的数据,其本身在将来被访问的概率高).

Read more »

【TP】19 Paging:Faster Translations

Posted on 2017-10-02 | Post modified 2019-11-16 | In OS | Visitors

TLB stands for translation-lookaside buffer.
A TLB is part of the chip’s memory-management unit (MMU), and is simply a hardware cache of popular virtual-to-physical address translations.; thus, a better name would be an address-translation cache

Upon each virtual memory reference, the hardware first checks the TLB to see if the desired translation is held therein; if so, the translation is performed (quickly) without having to consult the page table (which has all translations). Because of their tremendous performance impact, TLBs in a real sense make virtual memory possible. 有了 TLB,在访问 memory 的时候,如果 desired translation 在 TLB,则直接 translation,而不用经过 page table 的转义。

TLB Basic Algorithm

假设:

  1. linear page table
  2. a hardware-managed TLB
    Read more »

【TP】18 Introduction to Paging

Posted on 2017-10-01 | Post modified 2019-11-16 | In OS | Visitors

将 memory 分割成 fixed-sized 块,这就叫 paging

We divide address space into fixed-sized units, each of which we call a page. Correspondingly, we view physical memory as an array of fixed-sized slots called page frames.

A Simple Example And Overview

OS may find free spaces from a free list to your program, and there will be a mapping relationship between physical address and virtual address.


To record where each virtual page of the address space is placed in physical memory, the operating system usually keeps a per-process data structure known as a page table.

Read more »

Docker is not VM

Posted on 2017-09-21 | Post modified 2019-11-16 | In Technology | Visitors

I spend a good portion of my time at Docker talking to community members with varying degrees of familiarity with Docker and I sense a common theme: people’s natural response when first working with Docker is to try and frame it in terms of virtual machines. I can’t count the number of times I have heard Docker containers described as “lightweight VMs”.

I get it because I did the exact same thing when I first started working with Docker. It’s easy to connect those dots as both technologies share some characteristics. Both are designed to provide an isolated environment in which to run an application. Additionally, in both cases that environment is represented as a binary artifact that can be moved between hosts. There may be other similarities, but to me these are the two biggies.

Read more »

【WEP】Commodity Hardware Today

Posted on 2017-09-18 | Post modified 2019-11-16 | In OS | Visitors

Commodity Hardware today

Over the years personal computers and smaller servers standardized on a chipset with two parts: the Northbridge and Southbridge.

Figure 2.1

A couple of bottlenecks are immediately apparent in this design

RAM bandwidth 争抢 (DMA 允许 device 直接从 RAM 里读写数据,但是都要通过 Northbridge,这样就 CPU 通过 Northbridge 访问 RAM 的 bandwidth冲突)

In the earliest days of the PC, all communication with devices on either bridge had to pass through the CPU, negatively impacting overall system performance. To work around this problem some devices became capable of direct memory access (DMA). DMA allows devices, with the help of the Northbridge, to store and receive data in RAM directly without the intervention of the CPU (and its inherent performance cost). Today all high-performance devices attached to any of the buses can utilize DMA. While this greatly reduces the workload on the CPU, it also creates contention for the bandwidth of the Northbridge as DMA requests compete with RAM access from the CPUs.

Read more »
<1…678…10>
XS Zhao

XS Zhao

60 posts
12 categories
36 tags
GitHub Facebook Instagram E-Mail
Recent Posts
  1. Ethereum Project Infrastructure
  2. Dapp: Lottery Contract
  3. Write ethereum test code
  4. Review: bLSM:* A General Purpose Log Structured Merge Tree
  5. Review: ElasticBF: Fine-grained and Elastic Bloom Filter Towards Efficient Read for LSM-tree-based KV Stores
© 2017 - 2020 XS Zhao
Powered by Hexo
Theme - NexT.Muse
0%